The semiconductor industry has continually improved the processing capabilities and power consumption of integrated chips (ICs) by shrinking the minimum feature size of chip components through improvements in lithographic processes. However, in recent years process limitations have made it difficult to support the continued shrinking of minimum feature size. The vertical integration of ICs has emerged as a potential alternative approach to improving integrated chip performance. By vertically integrating IC die to behave as a single chip, metal interconnect distance is shortened, thereby improving processing capabilities and reducing power consumption.
In many vertically integrated IC structures, an interposer is configured to carry one or more IC die. The interposer provides for structural stability, improved heat dissipation, improved interconnection characteristics, etc. Micro-bumps connect respective IC die to through-silicon vias (TSV), which are vertical electrical connections extending through the interposer. In general, a TSV is comprised of a conductive metal, such as copper or tungsten, and is surrounded by a dielectric layer.